The present invention relates generally to semiconductor devices, and more specifically, to semiconductor devices having reduced source/drain contact resistance.
Recent semiconductor fabrication methods have been developed to introduce silicon germanium (SiGe) material into semiconductor devices, especially in p-type field effect transistor devices typically referred to as pFETs. The SiGe material is typically grown from an active layer of the semiconductor substrate reserved for the source/drain regions and allows for increased carrier mobility therethrough compared to pure silicon (Si). Accordingly, forming the source/drain regions of the pFET from SiGe can reduce the resistance at the source/drain regions thereby improving the overall performance of the device.
In addition to the carrier mobility enhancements provided by SiGe, recent trends in semiconductor manufacturing techniques have led to utilizing dopants typically included in the SiGe material to form extension regions in the underlying active semiconductor layer. Turning to FIG. 1, for example, a conventional semiconductor device 10 is illustrated. The conventional semiconductor device includes a semiconductor-on-insulator (SOI) substrate 12 and a gate structure 14 formed on an active layer 16 of the SOI substrate 12. Single-layer SiGe source/drain regions 18 are formed on an upper surface of the active layer 16 located adjacent opposing sides of the gate structure 14.
As illustrated in FIG. 2, the substrate 12 is exposed to a thermal anneal process such that dopants such as boron (B), for example, included in the single-layer SiGe source/drain regions 18 are driven into the underlying active layer 16. It has been discovered that some dopants such as boron diffuse from SiGe at a much slower rate compared to the diffusion of dopants from a pure semiconductor material such as silicon (Si), for example. The slow diffusion rate typically has a high thermal budget (high annealing temperature and/or long anneal time) results in the formation of gradient-shaped extension regions 20 (dopant gradient is greater than 5 nm/decade) within the active semiconductor layer 16. These gradient-shaped extension regions 20 are defined by the non-uniform step-like junctions that are located beneath the gate structure 14 as further illustrated in FIG. 2.